library ieee;
use ieee.std_logic_1164.all;

entity fullAdder32 is
	port (
		A, B : in bit_vector(31 downto 0);
		Cin : in bit;
		Sum : out bit_vector(31 downto 0);
		Cout : out bit
	);
end entity fullAdder32;

architecture STRUCTURAL of fullAdder32 is

	component fullAdder
		port(
			ina, inb, cin : in bit;
			sum, cout : out bit
	);
	end component;
	
	for all : fullAdder use entity work.fullAdder(DATAFLOW);
	
	signal Carry : bit_vector(30 downto 0);
	
begin

	fa_0 : fullAdder port map(A(0), B(0), Cin, Sum(0), Carry(0));
	
	adder : for i in 1 to 30 GENERATE
		fa : fullAdder port map(A(i), B(i), Carry(i-1), Sum(i), Carry(i));
	END GENERATE adder;

	fa_31 : fullAdder port map(A(31), B(31), Carry(30), Sum(31), Cout);

end architecture STRUCTURAL;
